1. Technical Field
The present invention relates generally to semiconductors and more specifically to an improved fabrication process for making semiconductor memory devices.
2. Background Art
Various types of memories have been developed in the past as electronic memory media for computers and similar systems. Such memories include electrically erasable programmable read only memory (EEPROM) and electrically programmable read only memory (EPROM). Each type of memory had advantages and disadvantages. EEPROM can be easily erased without extra exterior equipment but with reduced data storage density, lower speed, and higher cost. EPROM, in contrast, is less expensive and has greater density but lacks erasability.
A newer type of memory called xe2x80x9cFlashxe2x80x9d EEPROM, or Flash memory, has become extremely popular because it combines the advantages of the high density and low cost of EPROM with the electrical erasability of EEPROM. Flash memory can be rewritten and can hold its contents without power. It is used in many portable electronic products, such as cell phones, portable computers, voice recorders, etc. as well as in many larger electronic systems, such as cars, planes, industrial control systems, etc.
In Flash memory, bits of information are programmed individually as in the older types of memory, such as dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips. However, in DRAMs and SRAMs where individual bits can be erased one at a time, Flash memory must currently be erased in fixed multi-bit blocks or sectors.
Conventionally, Flash memory is constructed of many Flash memory cells where a single bit is stored in each memory cell and the cells are programmed by hot electron injection and erased by Fowler-Nordheim tunneling. However, increased market demand has driven the development of Flash memory cells to increase both the speed and the density. Newer Flash memory cells have been developed that allow more than a single bit to be stored in each cell.
One memory cell structure involves the storage of more than one level of charge to be stored in a memory cell with each level representative of a bit. This structure is referred to as a multi-level storage (MLS) architecture. Unfortunately, this structure inherently requires a great deal of precision in both programming and reading the differences in the levels to be able to distinguish the bits. If a memory cell using the MLS architecture is overcharged, even by a small amount, the only way to correct the bit error would be to erase the memory cell and totally reprogram the memory cell. The need in the MLS architecture to precisely control the amount of charge in a memory cell while programming also makes the technology slower and the data less reliable. It also takes longer to access or xe2x80x9creadxe2x80x9d0 precise amounts of charge. Thus, both speed and reliability are sacrificed in order to improve memory cell density.
An even newer technology known as xe2x80x9cMirrorBit(copyright)xe2x80x9d Flash memory has been developed which allows multiple bits to be stored in a single cell. In this technology, a memory cell is essentially split into two identical (mirrored) parts, each of which is formulated for storing one of two independent bits. Each MirrorBit Flash memory cell, like a traditional Flash cell, has a gate with a source and a drain. However, unlike a traditional Flash cell in which the source is always connected to an electrical source and the drain is always connected to an electrical drain, each MirrorBit Flash memory cell can have the connections of the source and drain reversed during operation to permit the storing of two bits.
The MirrorBit Flash memory cell has a semiconductor substrate with implanted conductive bitlines. A. multilayer storage layer, referred to as a xe2x80x9ccharge-trapping dielectric layerxe2x80x9d, is formed over the semiconductor substrate. The charge-trapping dielectric layer can generally be composed of three separate layers: a first insulating layer, a charge-trapping layer, and a second insulating layer. Wordlines are formed over the charge-trapping dielectric layer perpendicular to the bitlines. Programming circuitry controls two bits per cell by applying a signal to the wordline, which acts as a control gate, and changing bitline connections such that one bit is stored by source and drain being connected in one arrangement and a complementary bit is stored by the source and drain being interchanged in another arrangement.
Programming of the cell is accomplished in one direction and reading is accomplished in a direction opposite that in which it is programmed.
All memory cells including the MirrorBit Flash memory cells are made up of multiple layers of material, which are deposited on a semiconductor substrate. At the same time that the memory cells are being built up in high-density core regions, they are surrounded by low-density peripheral regions containing transistors for input/output circuitry and programming circuitry which are also built up layer upon layer on the semiconductor substrate. The various memory cells in the core and the transistors in the circuit are separated by areas of shallow trench isolation, as well as the individual transistors being separated by shallow trench isolations, which are regions of an insulator such as silicon oxide deposited in trenches in the semiconductor substrate.
As the memory and transistor devices have been made smaller, it has been discovered that it is necessary to have an extremely planar surface of the semiconductor substrate with the shallow trench isolations. Unfortunately, it has been found that the current chemical-mechanical polishing (CMP) processes cause dishing or concavities in the tops of the shallow trench isolations, which are relatively broad. This dishing subsequently results in uneven planarization and detrimentally affects the integrated circuit as a whole.
A solution to this problem has been long sought but has long eluded those skilled in the art.
The present invention provides a method of manufacturing an integrated circuit having a semiconductor wafer with a chemical-mechanical polishing stop layer deposited thereon. A first photoresist layer is processed over the chemical-mechanical polishing stop layer and is patterned with the semiconductor wafer to form a shallow trench. A shallow trench isolation material is deposited on the chemical-mechanical polishing stop layer and in the shallow trench. A second photoresist layer is processed over the shallow trench isolation material leaving the shallow trench uncovered. The uncovered shallow trench is then treated to form a chemical-mechanical polishing stop layer. The shallow trench isolation material is then chemical-mechanical polished to be co-planar with the chemical-mechanical stop layer and the chemical-mechanical polishing stop treated area.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings. dr
FIG. 1 is a plan view of a MirrorBit Flash EEPROM according to the present invention;
FIG. 2 is a cross-sectional view of a partially processed semiconductor wafer,
FIG. 3 is the structure of FIG. 2 after formation of the shallow trenches;
FIG. 4 is the structure of FIG. 3 after deposition of the insulation material on the wafer,
FIG. 5 is the structure of FIG. 4 after deposition and processing of a photoresist layer to form a reverse mask and treatment of the unmasked areas;
FIG. 6 is the structure of FIG. 5 after chemical-mechanical polishing;
FIG. 7 is the structure of FIG. 6 after removal of a chemical-mechanical polishing stop layer, and
FIG. 8 is a simplified flow chart according to the present invention.